/***************************************************************************
 *
 * Copyright 2015-2019 BES.
 * All rights reserved. All unpublished rights reserved.
 *
 * No part of this work may be used or reproduced in any form or by any
 * means, or stored in a database or retrieval system, without prior written
 * permission of BES.
 *
 * Use of this work is governed by a license granted by BES.
 * This work contains confidential and proprietary information of
 * BES. which is protected by copyright, trade secret,
 * trademark and other intellectual property rights.
 *
 ****************************************************************************/
#ifndef __REG_CODECIP_H_
#define __REG_CODECIP_H_

#include "plat_types.h"

#define CODECIP_FIFO_DEPTH 8

/* codecip register */
/* enable register */
#define CODECIP_ENABLE_REG_REG_OFFSET 0x0
#define CODECIP_ENABLE_REG_CODEC_ENABLE_SHIFT (0)
#define CODECIP_ENABLE_REG_CODEC_ENABLE_MASK ((0x1)<<CODECIP_ENABLE_REG_CODEC_ENABLE_SHIFT)

/* recv block fifo reset register */
#define CODECIP_RX_BLOCK_FIFO_RESET_REG_OFFSET 0x4
#define CODECIP_RX_BLOCK_FIFO_RESET_RESET_SHIFT (0)
#define CODECIP_RX_BLOCK_FIFO_RESET_RESET_MASK ((0x1)<<CODECIP_RX_BLOCK_FIFO_RESET_RESET_SHIFT)

/* send block fifo reset register */
#define CODECIP_TX_BLOCK_FIFO_RESET_REG_OFFSET 0x8
#define CODECIP_TX_BLOCK_FIFO_RESET_RESET_SHIFT (0)
#define CODECIP_TX_BLOCK_FIFO_RESET_RESET_MASK ((0x1)<<CODECIP_TX_BLOCK_FIFO_RESET_RESET_SHIFT)

/* recv buffer register */
#define CODECIP_RX_BUFF_REG_OFFSET 0xC

/* send buffer register */
#define CODECIP_TX_BUFF_REG_OFFSET 0xC

/* pcm config register */
#define CODECIP_CR_REG_OFFSET 0x10
#define CODECIP_CR_DUAL_MIC_ENABLE_SHIFT (5)
#define CODECIP_CR_DUAL_MIC_ENABLE_MASK ((0x1)<<CODECIP_CR_DUAL_MIC_ENABLE_SHIFT)
#define CODECIP_CR_16BIT_MODE_SHIFT (4)
#define CODECIP_CR_16BIT_MODE_MASK ((0x1)<<CODECIP_CR_16BIT_MODE_SHIFT)
#define CODECIP_CR_DAC_EXCHANGE_LR_SHIFT (3)
#define CODECIP_CR_DAC_EXCHANGE_LR_MASK ((0x1)<<CODECIP_CR_DAC_EXCHANGE_LR_SHIFT)
#define CODECIP_CR_DUAL_CHANNEL_DAC_SHIFT (2)
#define CODECIP_CR_DUAL_CHANNEL_DAC_MASK ((0x1)<<CODECIP_CR_DUAL_CHANNEL_DAC_SHIFT)
#define CODECIP_CR_DAC_ENABLE_SHIFT (1)
#define CODECIP_CR_DAC_ENABLE_MASK ((0x1)<<CODECIP_CR_DAC_ENABLE_SHIFT)
#define CODECIP_CR_ADC_ENABLE_SHIFT (0)
#define CODECIP_CR_ADC_ENABLE_MASK ((0x1)<<CODECIP_CR_ADC_ENABLE_SHIFT)

/* int status register */
#define CODECIP_INT_STATUS_REG_OFFSET 0x1C
#define CODECIP_INT_STATUS_TX_FIFO_OVER_SHIFT (5)
#define CODECIP_INT_STATUS_TX_FIFO_OVER_MASK ((0x1)<<CODECIP_INT_STATUS_TX_FIFO_OVER_SHIFT)
#define CODECIP_INT_STATUS_TX_FIFO_EMPTY_SHIFT (4)
#define CODECIP_INT_STATUS_TX_FIFO_EMPTY_MASK ((0x1)<<CODECIP_INT_STATUS_TX_FIFO_EMPTY_SHIFT)
#define CODECIP_INT_STATUS_RX_FIFO_OVER_SHIFT (1)
#define CODECIP_INT_STATUS_RX_FIFO_OVER_MASK ((0x1)<<CODECIP_INT_STATUS_RX_FIFO_OVER_SHIFT)
#define CODECIP_INT_STATUS_RX_FIFO_DA_SHIFT (0)
#define CODECIP_INT_STATUS_RX_FIFO_DA_MASK ((0x1)<<CODECIP_INT_STATUS_RX_FIFO_DA_SHIFT)

/* int mask register */
#define CODECIP_INT_MASK_REG_OFFSET 0x20
#define CODECIP_INT_MASK_TX_FIFO_OVER_SHIFT (5)
#define CODECIP_INT_MASK_TX_FIFO_OVER_MASK ((0x1)<<CODECIP_INT_MASK_TX_FIFO_OVER_SHIFT)
#define CODECIP_INT_MASK_TX_FIFO_EMPTY_SHIFT (4)
#define CODECIP_INT_MASK_TX_FIFO_EMPTY_MASK ((0x1)<<CODECIP_INT_MASK_TX_FIFO_EMPTY_SHIFT)
#define CODECIP_INT_MASK_RX_FIFO_OVER_SHIFT (1)
#define CODECIP_INT_MASK_RX_FIFO_OVER_MASK ((0x1)<<CODECIP_INT_MASK_RX_FIFO_OVER_SHIFT)
#define CODECIP_INT_MASK_RX_FIFO_DA_SHIFT (0)
#define CODECIP_INT_MASK_RX_FIFO_DA_MASK ((0x1)<<CODECIP_INT_MASK_RX_FIFO_DA_SHIFT)
#define CODECIP_INT_MASK_ALL \
    (CODECIP_INT_MASK_TX_FIFO_OVER_MASK|CODECIP_INT_MASK_TX_FIFO_EMPTY_MASK|CODECIP_INT_MASK_RX_FIFO_OVER_MASK|CODECIP_INT_MASK_RX_FIFO_DA_MASK)
#define CODECIP_INT_UNMASK_ALL 0

/* clr recv over flow register */
#define CODECIP_CLR_RX_OVER_FLOW_REG_OFFSET 0x24
#define CODECIP_CLR_RX_OVER_FLOW_CLR_SHIFT (0)
#define CODECIP_CLR_RX_OVER_FLOW_CLR_MASK ((0x1)<<CODECIP_CLR_RX_OVER_FLOW_CLR_SHIFT)

/* clr send over flow register */
#define CODECIP_CLR_TX_OVER_FLOW_REG_OFFSET 0x28
#define CODECIP_CLR_TX_OVER_FLOW_CLR_SHIFT (0)
#define CODECIP_CLR_TX_OVER_FLOW_CLR_MASK ((0x1)<<CODECIP_CLR_TX_OVER_FLOW_CLR_SHIFT)

/* recv fifo config register */
#define CODECIP_RX_FIFO_CFG_REG_OFFSET 0x2C
#define CODECIP_RX_FIFO_CFG_LEVEL_SHIFT (0)
#define CODECIP_RX_FIFO_CFG_LEVEL_MASK ((0xf)<<CODECIP_RX_FIFO_CFG_LEVEL_SHIFT)

/* send fifo config register */
#define CODECIP_TX_FIFO_CFG_REG_OFFSET 0x30
#define CODECIP_TX_FIFO_CFG_LEVEL_SHIFT (0)
#define CODECIP_TX_FIFO_CFG_LEVEL_MASK ((0xf)<<CODECIP_TX_FIFO_CFG_LEVEL_SHIFT)

/* dma ctrl register */
#define CODECIP_DMA_CTRL_REG_OFFSET 0x34
#define CODECIP_DMA_CTRL_CODEC_IF_ENABLE_SHIFT (2)
#define CODECIP_DMA_CTRL_CODEC_IF_ENABLE_MASK ((0x1)<<CODECIP_DMA_CTRL_CODEC_IF_ENABLE_SHIFT)
#define CODECIP_DMA_CTRL_TX_ENABLE_SHIFT (1)
#define CODECIP_DMA_CTRL_TX_ENABLE_MASK ((0x1)<<CODECIP_DMA_CTRL_TX_ENABLE_SHIFT)
#define CODECIP_DMA_CTRL_RX_ENABLE_SHIFT (0)
#define CODECIP_DMA_CTRL_RX_ENABLE_MASK ((0x1)<<CODECIP_DMA_CTRL_RX_ENABLE_SHIFT)

/* ramp config register */
#define CODECIP_RAMP_CFG_REG_OFFSET 0x40
#define CODECIP_RAMP_CFG_IND_SHIFT (31)
#define CODECIP_RAMP_CFG_IND_MASK ((0x1)<<CODECIP_RAMP_CFG_IND_SHIFT)
#define CODECIP_RAMP_CFG_BYPASS_SHIFT (30)
#define CODECIP_RAMP_CFG_BYPASS_MASK ((0x1)<<CODECIP_RAMP_CFG_BYPASS_SHIFT)
#define CODECIP_RAMP_CFG_PUP_STEP_SHIFT (23)
#define CODECIP_RAMP_CFG_PUP_STEP_MASK ((0x7f)<<CODECIP_RAMP_CFG_PUP_STEP_SHIFT)
#define CODECIP_RAMP_CFG_PDN_STEP_SHIFT (16)
#define CODECIP_RAMP_CFG_PDN_STEP_MASK ((0x7f)<<CODECIP_RAMP_CFG_PDN_STEP_SHIFT)

/* codec control register 1 */
#define CODECIP_CTRL1_REG_OFFSET 0x44
#define CODECIP_CTRL1_DAC_EN_SHIFT (30)
#define CODECIP_CTRL1_DAC_EN_MASK ((0x1)<<CODECIP_CTRL1_DAC_EN_SHIFT)
#define CODECIP_CTRL1_ADC_EN_SHIFT (29)
#define CODECIP_CTRL1_ADC_EN_MASK ((0x1)<<CODECIP_CTRL1_ADC_EN_SHIFT)
#define CODECIP_CTRL1_FF_FB_DIS_SHIFT (28)
#define CODECIP_CTRL1_FF_FB_DIS_MASK ((0x1)<<CODECIP_CTRL1_FF_FB_DIS_SHIFT)
#define CODECIP_CTRL1_STREE_EN_SHIFT (27)
#define CODECIP_CTRL1_STREE_EN_MASK ((0x1)<<CODECIP_CTRL1_STREE_EN_SHIFT)
#define CODECIP_CTRL1_SDITHER_BYPASS_SHIFT (26)
#define CODECIP_CTRL1_SDITHER_BYPASS_MASK ((0x1)<<CODECIP_CTRL1_SDITHER_BYPASS_SHIFT)
#define CODECIP_CTRL1_SADC_IN_INVERT_CH1_SHIFT (25)
#define CODECIP_CTRL1_SADC_IN_INVERT_CH1_MASK ((0x1)<<CODECIP_CTRL1_SADC_IN_INVERT_CH1_SHIFT)
#define CODECIP_CTRL1_SADC_IN_INVERT_CH0_SHIFT (24)
#define CODECIP_CTRL1_SADC_IN_INVERT_CH0_MASK ((0x1)<<CODECIP_CTRL1_SADC_IN_INVERT_CH0_SHIFT)
#define CODECIP_CTRL1_SADC_CLK_X2_MODE_SHIFT (18)
#define CODECIP_CTRL1_SADC_CLK_X2_MODE_MASK ((0x1)<<CODECIP_CTRL1_SADC_CLK_X2_MODE_SHIFT)
#define CODECIP_CTRL1_SDAC_R_GAIN10_SHIFT (11)
#define CODECIP_CTRL1_SDAC_R_GAIN10_MASK ((0x3)<<CODECIP_CTRL1_SDAC_R_GAIN10_SHIFT)
#define CODECIP_CTRL1_SDAC_R_VOL_SHIFT (6)
#define CODECIP_CTRL1_SDAC_R_VOL_MASK ((0x1f)<<CODECIP_CTRL1_SDAC_R_VOL_SHIFT)
#define CODECIP_CTRL1_DAC_UP_SEL_SHIFT (0)
#define CODECIP_CTRL1_DAC_UP_SEL_MASK ((0xf)<<CODECIP_CTRL1_DAC_UP_SEL_SHIFT)

/* codec control register 2 */
#define CODECIP_CTRL2_REG_OFFSET 0x48
#define CODECIP_CTRL2_DITHER_GAIN20_SHIFT (29)
#define CODECIP_CTRL2_DITHER_GAIN20_MASK ((0x7)<<CODECIP_CTRL2_DITHER_GAIN20_SHIFT)
#define CODECIP_CTRL2_SADC_VOL_CH0_SHIFT (25)
#define CODECIP_CTRL2_SADC_VOL_CH0_MASK ((0xf)<<CODECIP_CTRL2_SADC_VOL_CH0_SHIFT)
#define CODECIP_CTRL2_SDAC1K_SHIFT (24)
#define CODECIP_CTRL2_SDAC1K_MASK ((0x1)<<CODECIP_CTRL2_SDAC1K_SHIFT)
#define CODECIP_CTRL2_SLOOP_SHIFT (23)
#define CODECIP_CTRL2_SLOOP_MASK ((0x1)<<CODECIP_CTRL2_SLOOP_SHIFT)
#define CODECIP_CTRL2_TPORTS_CODEC_TEST_EN_SHIFT (22)
#define CODECIP_CTRL2_TPORTS_CODEC_TEST_EN_MASK ((0x1)<<CODECIP_CTRL2_TPORTS_CODEC_TEST_EN_SHIFT)
#define CODECIP_CTRL2_TPORTS_SEL_SHIFT (17)
#define CODECIP_CTRL2_TPORTS_SEL_MASK ((0x1f)<<CODECIP_CTRL2_TPORTS_SEL_SHIFT)
#define CODECIP_CTRL2_SADC_DVST_CTRL_SHIFT (12)
#define CODECIP_CTRL2_SADC_DVST_CTRL_MASK ((0x1f)<<CODECIP_CTRL2_SADC_DVST_CTRL_SHIFT)
#define CODECIP_CTRL2_SDM_GAIN_SHIFT (10)
#define CODECIP_CTRL2_SDM_GAIN_MASK ((0x3)<<CODECIP_CTRL2_SDM_GAIN_SHIFT)
#define CODECIP_CTRL2_DITHER_GAIN43_SHIFT (8)
#define CODECIP_CTRL2_DITHER_GAIN43_MASK ((0x3)<<CODECIP_CTRL2_DITHER_GAIN43_SHIFT)
#define CODECIP_CTRL2_SDAC_L_VOL_SHIFT (2)
#define CODECIP_CTRL2_SDAC_L_VOL_MASK ((0x1f)<<CODECIP_CTRL2_SDAC_L_VOL_SHIFT)
#define CODECIP_CTRL2_SMUTE_L_SHIFT (1)
#define CODECIP_CTRL2_SMUTE_L_MASK ((0x1)<<CODECIP_CTRL2_SMUTE_L_SHIFT)
#define CODECIP_CTRL2_SMUTE_R_SHIFT (0)
#define CODECIP_CTRL2_SMUTE_R_MASK ((0x1)<<CODECIP_CTRL2_SMUTE_R_SHIFT)

/* codec control register 3 */
#define CODECIP_CTRL3_REG_OFFSET 0x4C
#define CODECIP_CTRL3_DEEMPA_AL3_DACFIFO_BYPASS_SHIFT (15)
#define CODECIP_CTRL3_DEEMPA_AL3_DACFIFO_BYPASS_MASK ((0x1)<<CODECIP_CTRL3_DEEMPA_AL3_DACFIFO_BYPASS_SHIFT)
#define CODECIP_CTRL3_DEEMPA_AL2_DACFIFO_ERR_CLR_EN_SHIFT (14)
#define CODECIP_CTRL3_DEEMPA_AL2_DACFIFO_ERR_CLR_EN_MASK ((0x1)<<CODECIP_CTRL3_DEEMPA_AL2_DACFIFO_ERR_CLR_EN_SHIFT)
#define CODECIP_CTRL3_DEEMPA_AL1_ADC_FIFO_BYPASS_SHIFT (13)
#define CODECIP_CTRL3_DEEMPA_AL1_ADC_FIFO_BYPASS_MASK ((0x1)<<CODECIP_CTRL3_DEEMPA_AL1_ADC_FIFO_BYPASS_SHIFT)
#define CODECIP_CTRL3_DEEMPA_AL0_ADCFIFO_ERR_CLR_EN_SHIFT (12)
#define CODECIP_CTRL3_DEEMPA_AL0_ADCFIFO_ERR_CLR_EN_MASK ((0x1)<<CODECIP_CTRL3_DEEMPA_AL0_ADCFIFO_ERR_CLR_EN_SHIFT)
#define CODECIP_CTRL3_SDAC_L_GAIN10_SHIFT (10)
#define CODECIP_CTRL3_SDAC_L_GAIN10_MASK ((0x3)<<CODECIP_CTRL3_SDAC_L_GAIN10_SHIFT)
#define CODECIP_CTRL3_SDAC_OSR_SEL_SHIFT (7)
#define CODECIP_CTRL3_SDAC_OSR_SEL_MASK ((0x3)<<CODECIP_CTRL3_SDAC_OSR_SEL_SHIFT)
#define CODECIP_CTRL3_SFS_SEL_SHIFT (0)
#define CODECIP_CTRL3_SFS_SEL_MASK ((0xf)<<CODECIP_CTRL3_SFS_SEL_SHIFT)

/* codec control register 4 */
#define CODECIP_CTRL4_REG_OFFSET 0x50
#define CODECIP_CTRL4_ADC_HBF3_SEL_CH1_SHIFT (27)
#define CODECIP_CTRL4_ADC_HBF3_SEL_CH1_MASK ((0x7)<<CODECIP_CTRL4_ADC_HBF3_SEL_CH1_SHIFT)
#define CODECIP_CTRL4_ADC_HBF3_SEL_CH0_SHIFT (24)
#define CODECIP_CTRL4_ADC_HBF3_SEL_CH0_MASK ((0x7)<<CODECIP_CTRL4_ADC_HBF3_SEL_CH0_SHIFT)
#define CODECIP_CTRL4_ADC_ANC_SEL_CH1_SHIFT (23)
#define CODECIP_CTRL4_ADC_ANC_SEL_CH1_MASK ((0x1)<<CODECIP_CTRL4_ADC_ANC_SEL_CH1_SHIFT)
#define CODECIP_CTRL4_ADC_ANC_SEL_CH0_SHIFT (22)
#define CODECIP_CTRL4_ADC_ANC_SEL_CH0_MASK ((0x1)<<CODECIP_CTRL4_ADC_ANC_SEL_CH0_SHIFT)
#define CODECIP_CTRL4_ADC_DOWN_SEL_SHIFT (20)
#define CODECIP_CTRL4_ADC_DOWN_SEL_MASK ((0x3)<<CODECIP_CTRL4_ADC_DOWN_SEL_SHIFT)
#define CODECIP_CTRL4_HSR_SEL_CH1_SHIFT (19)
#define CODECIP_CTRL4_HSR_SEL_CH1_MASK ((0x1)<<CODECIP_CTRL4_HSR_SEL_CH1_SHIFT)
#define CODECIP_CTRL4_HSR_SEL_CH0_SHIFT (18)
#define CODECIP_CTRL4_HSR_SEL_CH0_MASK ((0x1)<<CODECIP_CTRL4_HSR_SEL_CH0_SHIFT)
#define CODECIP_CTRL4_SIDETONE_MIC_SEL_SHIFT (17)
#define CODECIP_CTRL4_SIDETONE_MIC_SEL_MASK ((0x1)<<CODECIP_CTRL4_SIDETONE_MIC_SEL_SHIFT)
#define CODECIP_CTRL4_DUAL_CH_DAC_SHIFT (16)
#define CODECIP_CTRL4_DUAL_CH_DAC_MASK ((0x1)<<CODECIP_CTRL4_DUAL_CH_DAC_SHIFT)
#define CODECIP_CTRL4_DUAL_CH_ADC_SHIFT (15)
#define CODECIP_CTRL4_DUAL_CH_ADC_MASK ((0x1)<<CODECIP_CTRL4_DUAL_CH_ADC_SHIFT)
#define CODECIP_CTRL4_DAC_GAIN_SEL_SHIFT (14)
#define CODECIP_CTRL4_DAC_GAIN_SEL_MASK ((0x1)<<CODECIP_CTRL4_DAC_GAIN_SEL_SHIFT)
#define CODECIP_CTRL4_ADC_GAIN_SEL_SHIFT (13)
#define CODECIP_CTRL4_ADC_GAIN_SEL_MASK ((0x1)<<CODECIP_CTRL4_DAC_GAIN_SEL_SHIFT)
#define CODECIP_CTRL4_ADC_LR_SWAP_SHIFT (12)
#define CODECIP_CTRL4_ADC_LR_SWAP_MASK ((0x1)<<CODECIP_CTRL4_ADC_LR_SWAP_SHIFT)
#define CODECIP_CTRL4_DAC_LR_SWAP_SHIFT (11)
#define CODECIP_CTRL4_DAC_LR_SWAP_MASK ((0x1)<<CODECIP_CTRL4_DAC_LR_SWAP_SHIFT)
#define CODECIP_CTRL4_SADC_VOL_CH1_SHIFT (7)
#define CODECIP_CTRL4_SADC_VOL_CH1_MASK ((0xf)<<CODECIP_CTRL4_SADC_VOL_CH1_SHIFT)
#define CODECIP_CTRL4_PDM_CAP_INV_CH1_SHIFT (6)
#define CODECIP_CTRL4_PDM_CAP_INV_CH1_MASK ((0x1)<<CODECIP_CTRL4_PDM_CAP_INV_CH1_SHIFT)
#define CODECIP_CTRL4_PDM_CAP_INV_CH0_SHIFT (5)
#define CODECIP_CTRL4_PDM_CAP_INV_CH0_MASK ((0x1)<<CODECIP_CTRL4_PDM_CAP_INV_CH0_SHIFT)
#define CODECIP_CTRL4_PDM_ADC_SEL_CH1_SHIFT (4)
#define CODECIP_CTRL4_PDM_ADC_SEL_CH1_MASK ((0x1)<<CODECIP_CTRL4_PDM_ADC_SEL_CH1_SHIFT)
#define CODECIP_CTRL4_PDM_ADC_SEL_CH0_SHIFT (3)
#define CODECIP_CTRL4_PDM_ADC_SEL_CH0_MASK ((0x1)<<CODECIP_CTRL4_PDM_ADC_SEL_CH0_SHIFT)
#define CODECIP_CTRL4_PDM_DATA_INV_SHIFT (1)
#define CODECIP_CTRL4_PDM_DATA_INV_MASK ((0x1)<<CODECIP_CTRL4_PDM_DATA_INV_SHIFT)
#define CODECIP_CTRL4_PDM_ENABLE_SHIFT (0)
#define CODECIP_CTRL4_PDM_ENABLE_MASK ((0x1)<<CODECIP_CTRL4_PDM_ENABLE_SHIFT)

#endif /* __REG_CODECIP_H_ */
